|Everything You Wanted to Know About SDRAM|
By Craig Taylor
In this segment we will attempt to answer, in a simple way, the following questions:
As a PC memory customer, you may not have heard of us before. Enhanced Memory Systems is a supplier of high speed, low latency DRAMs to the world of embedded computing. Embedded computers are specific purpose computers and are not usually required to run Windows or office programs and certainly not games. They are, rather, the compute engines that run routers and switches in the communications industry. They also run your car which is the reason we cant fix our own cars these days (we can be thankful they work better).
Our customers in the past have been skilled engineers building complex systems so our discussions regarding our products and their benefits tended to start at a different technical level. It has become apparent that the computer world in general has done a poor job of explaining the memory technology used in a PC and just what all this jargon means (Intel likes it that way). Just what the heck is synchronous memory? What happened to EDO? What was EDO? How do you get from 133 MHz to 7.5 ns? What is CAS Latency? What is clock access time and why should I care? Etc.
I certainly cant demystify the whole world of memory technology without boring everyone (except the technocrats) to tears. I will attempt to do little pieces with a minimum of technical jargon and almost no math. We will start with the SDRAM.
SDRAM does not stand for S - dram because a dram is a very small unit of measure and may have derivation from Drachma which is the Greek currency which is also small (319 to the Dollar). SDRAM actually stands for Synchronous Dynamic Random Access Memory. I will leave discussion of dynamic memory technology for another day and talk here about synchronous memory technology.
Synchronous means that all memory transactions are relative to a clock. If you look at a DIMM pin definition you find CK0, CK1, CK2, CK3. These are the clock inputs for the memory devices on the DIMM. A clock, for digital circuits, is simply an oscillator that moves between 0 Volts and Vcc (the supply voltage required for the chip, generally 3.3V) at regular intervals as described below:
The clock frequency is measured in Hertz which means cycles per second and has nothing to do with rental cars. The period of the clock is the time taken to complete one cycle and is the inverse of the frequency. For example:
50 Hertz is 50 cycles per second that has a period of 1/50 or .02 seconds
Our HSDRAM runs at 133 MHz+ which is 133 million cycles per second or 133 x 106 cycles per second. The period therefore is 1/133,000,000 or 1/133x106 or .0000000075 or 7.5 x10-9 seconds or 7.5 nanoseconds (a nanosecond is equal to 10-9 seconds). Our HSDRAM is marked with a -7.5 (SM12808DT-7.5) which is the specification for the minimum period of the clock and the minimum amount of time between data accesses. A higher frequency clock therefore would have a smaller period. In the system both the chipset and the memory use the same clock hence they are synchronized.
A complete description of SDRAM architecture requires some basic understanding of DRAM operation which is better done in small bits which will follow in weeks to come. Suffice it to say that in a PC when the processor wants data from the memory (output bus), the chipset generates commands which go to the DIMM module (input bus). The command to read memory must arrive at the memory before a rising edge of the clock and persist for some length of time. The memory will then output data sometime before a rising edge of the clock and the data will persist for some length of time. This can be diagramed as follows:
You may have noticed CL2 in the diagram. This stands for CAS Latency of 2 which simply means that if you set your machine up for CL2 the chipset is expecting the data on the second rising edge of the clock after the command to read. If the data does not arrive on the second rising edge of the clock the "blue screen of death" is a likely symptom. CAS stands for Column Address Strobe, the explanation of which will follow in my next paper "DRAMs Without the Detail".
Were not done yet because we havent talked about clock access time (tAC). In the system, clock access time can limit the maximum frequency for stable operation especially as you increase the load. The specification for this parameter is the maximum amount of time it takes from the rising edge of the clock to valid data on the output of the memory (see Fig.3).
The clock access time has to be less than the period because if it is greater than the period the data will arrive after the second rising edge of the clock which is likely to cause problems. There is another problem with systems running at high frequencies due to the fact that the command (read) signal originates at the chipset and must travel to the memory and the data must travel back to the chipset. You may say "so what" but Einstein says traveling faster then the speed of light is a problem. Well guess what? The speed of light is about 83 picoseconds per inch which is .083 nanoseconds (a picosecond is 10-12 or .000000000001 seconds) in a vacuum. A signal traveling on a trace on a printed circuit board is delayed 200 ps (.2 ns) per inch or more. This simply means that there is a propagation delay for all signals on a printed circuit board and the higher the frequency the more it matters. Is that it? Unfortunately theres more, but stay with me.
Since the pins on the memory must be at high voltage or zero volts (1 or 0) they must be able to switch between 0V and 3.3V. The rate of change of the voltage is dependent on the load (capacitance). Since a memory chip in its simplest form is a capacitor, as you add DIMMs to the system you add capacitance. The rate of change of a signal is given by the formula:
i = C dv/dt
I know I promised no math, not to mention Calculus but this simply means that the rate of change of a signal (dv/dt) is dependent on the current (i) and the capacitance (C). So as you add capacitance it takes longer to change from a 0 to a 1.
Remember that the data from the memory must arrive at the chip set before the rising edge of the clock, therefore memories with faster clock access time will be less sensitive to load and propagation delay.
Are we done yet? We could be but it isnt really true that the data can arrive at the chipset right at the end of the period. It is the same reason we all cant hit a 90 mile per hour fastball (I cant even hit the 60 mph ball from the machine in the batting cage). All chips, memories, microprocessors, etc. have setup time requirements. The data must travel from the memory to the chipset and give the chipset enough time to capture the data just like a batter must have enough time to get the bat around on a fastball (imagine how boring baseball would get if we move the pitchers mound in 10 feet). This all creates a window of opportunity for a system to work. The following is the whole thing in a nutshell:
There are many things that can be done in the system to compensate for these effects although even the most clever designers have yet to discover a way to defeat the speed of light. The best solution is to bring out the data faster. Our HSDRAM provides improved clock access time (TAC = 4.6 ns) and margin to most other parameters at 133 MHz. This is why our memory tends to be more stable under overclocked conditions.